Different types of memory are used in electronic apparatus for various purposes. Read only memory (ROM) and random-access memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for powering-up an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refresh, making it faster. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants (PDAs).
A typical SRAM device includes a matrix of addressable memory cells arranged in columns and rows. A typical SRAM cell includes two access transistors and a flip-flop formed with two cross-coupled inverters, each inverter having a pull-down (driver) and a pull-up (load) transistor. The gates of the access transistors in each row are connected to a word line and the sources of each of the access transistors in each column are connected to either one of a bit line pair, B or {overscore (B)}. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the SRAM cells.
Generally, to read data from an SRAM cell, a word line driver may activate a word line according to an address decoded by a row decoder and received via a signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bit line pair sending signals representing the data in the SRAM cell to a sense amplifier coupled to the bit line pair. The sense amplifier amplifies the potential difference on the bit line pair. Data from the sense amplifier is output to the external circuitry of the associated electronic apparatus optionally through a buffer. Essentially, data is written to each SRAM cell in the opposite way.
As mentioned above, to retain the data written to the matrix of SRAM cells, or memory array, each SRAM cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, wireless apparatus may be transitioned from an active mode to a standby mode of lower power consumption. As transistor size continues to diminish (e.g., 90 nm transistors), current leakage may be unacceptably high even during standby mode, requiring a transition to a still lower power consumption level, sleep mode, to conserve power adequately. Current leakage is often a combination of subthreshold leakage current, gate leakage current, and source/drain-to-body diode leakage current from the SRAM cell transistors. To reduce the current leakage, the battery-powered wireless apparatus may power-down the row and column circuitry associated with the memory array and enter the sleep mode while still supplying sufficient voltage across the memory array to retain data.
Presently, various powering-down designs for the peripheral circuitry are used. Typically, each of the various designs seek a balance among complexity, reliability and power consumption during the sleep mode. To achieve minimum power during the sleep mode, all of the periphery circuitry may be powered-down while sufficient supply voltage across the memory array is maintained. Additionally, powering-down designs may also strive to reduce voltage fluctuations, or “wiggling,” of word lines caused by the peripheral circuitry while transitioning from standby to sleep mode to prevent possible corruption of the data. Once the sleep mode has been entered, additional problems may be encountered. For example, currents may leak from the powered memory array to the peripheral circuitry associated with the columns that is not powered (shut down).
One existing design to minimize memory array leakage during sleep mode calls for lowering the memory array high voltage supply, VDDA. Additionally, a well voltage of the memory array transistors, more specifically Vnwell, may be set higher than the VDDA to reduce memory array leakage current. Other leakage reduction designs are also employed.
For example, the memory array low voltage supply, VSSA, can be raised and the bit lines floated (at a floating voltage typically near the raised VSSA, level) or clamped at the raised VSSA level while the word lines are maintained at about the VSSA level. To float the bit lines, main column peripheral circuits can be isolated from the bit lines by inserting isolation transistors in series with pre-charge circuitry, write circuitry and column multiplexer for each bit line. Preferably, the word line does not go much higher above the raised VSSA and the bit lines do not go much below the raised VSSA.
As the array leakage is minimized with the above aggressive approaches, periphery leakage can start to dominate the SRAM leakage during sleep mode at standard periphery bias conditions. A significant amount of gate and subthreshold current leakage among some of the large column periphery transistors whose gate, drain, and source are at different potentials (e.g., 0.8 volts versus 0.0 volts) may still occur. For example, existing SRAM devices often include a word line keeper in conjunction with a header and a footer for the word line driver that results in significant leakage through the gate of the word line driver due to the associated large gate area along a boundary of the voltage domains created by the header and the footer.
Accordingly, what is needed in the art is an improved low-power SRAM device that has minimum current leakage during sleep mode. More specifically, what is needed is a SRAM device that reduces leakage current of the SRAM array and the peripheral circuitry while in a sleep mode.